Existing machines are known to operate in superscalar mode in which two or more instructions are fetched from a program memory in the same machine cycle and then executed by different execution units. Commonly such instructions are located in adjacent memory positions and fetched from memory by a single fetch operation. Machines are also known to operate in very long instruction word (VLIW) mode. Such words may include a larger number of instructions retrieved from memory as a single word at a single word address. Instructions which may be included together in a single VLIW instruction are carefully controlled by software techniques to ensure that they avoid compatibility or data dependency problems between the instructions forming the word.
It is an object of the present invention to provide a computer system in which both superscalar and VLIW instruction modes can be handled with instruction scheduling to handle data dependencies between different instructions. Embodiments of the invention may provide a very high rate of instruction execution while avoiding a complex programming model for the software tool chain and assembly programmer.
In real-time operation the instruction scheduling should be deterministic ie that the hardware does not do too much “intelligent” rescheduling of instructions which are uncontrollable (and non-deterministic) because this makes the programmer/software toolchain's task extremely difficult when the real-time nature of the application has to be respected.